PCSX2 Documentation/PS2 VU (Vector Unit) Documentation Part 1: Difference between revisions
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PCSX2 Documentation/PS2 VU (Vector Unit) Documentation Part 1 (view source)
Revision as of 19:07, 19 July 2015
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Example | Example | ||
<source lang="asm"> | |||
IAND: | IAND: | ||
1000000 | 0000 | it x 5 | is x 5 | id x 5 | 110100 | 1000000 | 0000 | it x 5 | is x 5 | id x 5 | 110100 | ||
</source> | |||
If for 'id' we have '18', then the destination would be | If for 'id' we have '18', then the destination would be | ||
<source lang="asm"> | |||
18 &= 0xf; | 18 &= 0xf; | ||
</source> | |||
Resulting in the destination reg being vi02. | Resulting in the destination reg being vi02. | ||
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Example: | Example: | ||
<source lang="asm"> | |||
IADDIU vi05, vi00, 100 | IADDIU vi05, vi00, 100 | ||
IBNE vi05, vi00 <---- vi05's value is before the 100 was added | IBNE vi05, vi00 <---- vi05's value is before the 100 was added | ||
</source> | |||
The only exception to this are Flag reading lower instructions (FSxxx/FMxxx/FCxxx). In those cases the current value is read. | The only exception to this are Flag reading lower instructions (FSxxx/FMxxx/FCxxx). In those cases the current value is read. | ||
<source lang="asm"> | |||
FSAND vi05, 0xfff | FSAND vi05, 0xfff | ||
IBNE vi05, vi00 <---- vi05's value is the Status Reg | IBNE vi05, vi00 <---- vi05's value is the Status Reg | ||
</source> | |||
The situation becomes complex however when a VI reg is read AND written to in a sequence of instructions. | The situation becomes complex however when a VI reg is read AND written to in a sequence of instructions. | ||
<source lang="asm"> | |||
IADDIU vi05, vi00, 100 | IADDIU vi05, vi00, 100 | ||
IADDIU vi05, vi05, 100 | IADDIU vi05, vi05, 100 | ||
| Line 50: | Line 55: | ||
IADDIU vi05, vi05, 100 | IADDIU vi05, vi05, 100 | ||
IBNE vi05, vi00 <---- vi05's value is before any 100 value was added. (the value before the first IADDIU) | IBNE vi05, vi00 <---- vi05's value is before any 100 value was added. (the value before the first IADDIU) | ||
</source> | |||
When a VI reg is first written to, a 'chain' starts, and then if the next instruction reads AND writes to the same VI reg, the chain continues. It does this for a maximum of 4 instructions (the example above is the maximum). Then when the branch comes, the value that should be read is the value before the chain! | When a VI reg is first written to, a 'chain' starts, and then if the next instruction reads AND writes to the same VI reg, the chain continues. It does this for a maximum of 4 instructions (the example above is the maximum). Then when the branch comes, the value that should be read is the value before the chain! | ||
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It does: | It does: | ||
<source lang="asm"> | |||
[08b0] (000002ff) NOP | [08b0] (000002ff) NOP | ||
[08b0] (100310fb) IADDIU vi03, vi02, 251 | [08b0] (100310fb) IADDIU vi03, vi02, 251 | ||
| Line 72: | Line 78: | ||
[08d8] (000002ff) NOP | [08d8] (000002ff) NOP | ||
[08d8] (81e2bb7d) SQI.xyzw vf23, vi02++ | [08d8] (81e2bb7d) SQI.xyzw vf23, vi02++ | ||
</source> | |||
The first time the above block of code is run, the IBNE value for vi02 is the same value as it's value at [08b0] (before the chain starts). | The first time the above block of code is run, the IBNE value for vi02 is the same value as it's value at [08b0] (before the chain starts). | ||
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Example: | Example: | ||
<source lang="asm"> | |||
MAX vf02.x, vf00.x, vf01.x | MAX vf02.x, vf00.x, vf01.x | ||
</source> | |||
Assuming vf01.x holds a positive denormal, the result in vf02.x will be that same denormal. | Assuming vf01.x holds a positive denormal, the result in vf02.x will be that same denormal. | ||
Using SSE with DaZ however will just make the result '0' in that case (which is incorrect). | Using SSE with DaZ however will just make the result '0' in that case (which is incorrect). | ||
Some games rely on this correct behavior for MAX/MINI or else have graphical problems | Some games rely on this correct behavior for MAX/MINI or else have graphical problems :) | ||