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{{DocTabs|Section=3}}
   
''Originally written by cottonvibes''
 
''Originally written by cottonvibes''
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Since these articles are intended to describe advance secrets, I will not bother to explain common concepts about the VUs, and reading this implies you have at least an intermediate level of how the VUs work or how to program for them.
 
Since these articles are intended to describe advance secrets, I will not bother to explain common concepts about the VUs, and reading this implies you have at least an intermediate level of how the VUs work or how to program for them.
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==Note 1: VI lower instructions==
Note 1: VI lower instructions
      
For lower opcode operations dealing with VI regs, there is a 5 bit range for VI operands. But only VI regs 0 to 15 are accessible, for values greater than 15, the value is ANDed with 0xf. So effectively there is only a 4 bit range.
 
For lower opcode operations dealing with VI regs, there is a 5 bit range for VI operands. But only VI regs 0 to 15 are accessible, for values greater than 15, the value is ANDed with 0xf. So effectively there is only a 4 bit range.
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Resulting in the destination reg being vi02.
 
Resulting in the destination reg being vi02.
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Note 2: VI Reg Delays on Conditional Branches
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==Note 2: VI Reg Delays on Conditional Branches==
    
If a VI integer reg is modified before a conditional branch, the previous value of the integer is used for the calculation.
 
If a VI integer reg is modified before a conditional branch, the previous value of the integer is used for the calculation.
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Currently I'm not 100% sure what happens if a stall occurs in one of these VI chains, but I'm 95% sure it breaks the chain, making it start on the instruction where the stall occurred (wouldn't make sense otherwise).
 
Currently I'm not 100% sure what happens if a stall occurs in one of these VI chains, but I'm 95% sure it breaks the chain, making it start on the instruction where the stall occurred (wouldn't make sense otherwise).
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Note 3: ADD/SUB Precision and Normalization
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==Note 3: ADD/SUB Precision and Normalization==
    
When performing ADD/SUB operations, the ps2 VU's and the FPU act closely to SSE's "Round to Zero" mode (but of course they don't support INF/NaNs).  
 
When performing ADD/SUB operations, the ps2 VU's and the FPU act closely to SSE's "Round to Zero" mode (but of course they don't support INF/NaNs).  
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By using a custom ADD routine Nneeve wrote that simulates only 1 guard bit during single-precision float mantissa normalization, pcsx2 is able to boot and run Triace games with a playable status. (Refer to pcsx2's source for the custom routines)
 
By using a custom ADD routine Nneeve wrote that simulates only 1 guard bit during single-precision float mantissa normalization, pcsx2 is able to boot and run Triace games with a playable status. (Refer to pcsx2's source for the custom routines)
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Note 4: MAX/MINI with Denormals
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==Note 4: MAX/MINI with Denormals==
    
The ps2's Max and Min logic compares and transfers denormals to the result, as opposed to SSE with DaZ On which will treat any Denormal as Zero and just transfer Zero as the result.
 
The ps2's Max and Min logic compares and transfers denormals to the result, as opposed to SSE with DaZ On which will treat any Denormal as Zero and just transfer Zero as the result.
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Nneeve, Tmkk, Rama, and ZeroFrog who all helped in finding some of the secrets described in this documentation.
 
Nneeve, Tmkk, Rama, and ZeroFrog who all helped in finding some of the secrets described in this documentation.
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